Electrostatic Discharge (ESD) is a major source of reliability failures in integrated circuits (ICs). ESD arises when electrostatic charge accumulated in an object, such as a human body or a piece of equipment, is conducted and discharged into a second object, such as a circuit board or IC. This conduction of charge often results in damage to ICs, whether through electrical over-voltage stress or through thermal stress caused by large currents.
The severity of an ESD event can often be reduced by reducing the potential for electrostatic charge to build up, by controlling humidity in lab environments. However, the potential can never be completely mitigated. As a result, ICs are required to incorporate ESD protection structures, allowing them to tolerate a certain level of ESD in order to avoid reliability hazards.
FIG. 1 illustrates a conventional ESD protection circuit 100 of a device incorporating an input/output (I/O) circuitry 101, a single positive power supply VDD 102, and a negative power supply VSS 103. A signal 104 is protected to both VDD and VSS by primary positive and negative clamp structures 105 and 106, respectively. A series resistor RESD and secondary positive and negative clamps 107 and 108 further reduce the voltage at the I/O circuitry 101. The I/O circuitry 101 is connected to the device core circuitry 109. A power clamp 110 is placed between the VDD and VSS rails. The schematic shown in FIG. 1 shows all the major components used in an ESD protection circuit 100. However, it is known to someone skilled in the art that not all ESD protection circuits include all of these components. More complex strategies involving multiple positive and/or negative supply rails require more components.
The intention of the various clamps 105 to 108 shown in FIG. 1 is to shunt any ESD current seen at any pin away from the I/O 101 and core circuitry 109, providing a low-impedance path through the device, thereby avoiding any over-voltage stress on the I/O 101 and core circuitry 109. At the same time, the clamps must be designed appropriately such that they can handle the ESD current and are not themselves damaged by thermal over-stress caused by the large ESD currents.
The inclusion of an ESD protection circuit into an IC has a significant cost, both in area and cost of manufacturing, as well as in performance, i.e. speed and signal integrity. The area and cost issues are caused by the size of the various clamps used, which are often physically large. Accordingly, the ESD protection circuit constitutes a significant fraction of the total area of an integrated circuit. Therefore, the cost of the integrated circuit is directly impacted by the requirement for ESD tolerance. With regard to performance, the clamps act as parasitic capacitances due to their large size, which reduces the speed at which the signals to which they are attached can be driven. These parasitic capacitances can also cause signal integrity issues on signal traces due to increased reflections. As a result of both of these reasons, there is a significant incentive to reduce the size of the ESD clamps.
The simplest and arguably most common ESD structure commonly used for constructing ESD clamps is the diode. The diode is commonly built as a simple P-N junction (either a p-type diffusion in an n-well, or an n-type diffusion in a p-well). It is simple, has a very high current carrying capacity per unit area, and is easy to simulate. In many ways, the diode is the ideal clamp, but usually only in one direction. The other direction might also clamp depending on the type of diode. For example a Zener diode would clamp in both directions, but this is not commonly used in a CMOS process. As a result, most realizable ESD protection strategies that use diodes also require one or more of the other structures described earlier.
A first structure using MOS devices for ESD clamps, known as the “Big FET” approach, uses a trigger circuit to turn on a very large MOS device to conduct current during the ESD event. This approach has been used successfully to construct power clamps for many devices, and is particularly desired from a simulation perspective because no parasitic devices are involved, which therefore means that it can be simulated in a standard SPICE (Simulation Program with Integrated Circuit Emphasis)-compatible simulator. However, the MOS device is a surface conduction device, and its current carrying capacity is relatively small per unit area. As a result of this, the area required by the Big FET structure is often significantly larger than that required for either the snapback or Silicon-Controlled Rectifier (SCR) structures described below.
A “snapback” device is used in MOS devices, and makes use of the parasitic lateral NPN bipolar device that is inherent to all NMOS devices. FIG. 2 illustrates an NMOS device 200 with parasitic NPN device 201. The base 202 of the NPN is the bulk B of the NMOS device, while the emitter 203 and collector 204 of the NPN are source S and the drain D and of the NMOS device, respectively. During the ESD event, the parasitic NPN bipolar transistor 201 turns on, conducting the ESD current. This device can conduct a larger current per unit area than surface-conduction structures like the Big FET approach. The snapback device is advantageous because it can be made self-triggering and can also be used as the output device for standard CMOS I/O structures, thereby making “self-protecting” I/Os.
FIG. 3 shows a layout and cross sectional view of a snapback device in a reasonably advanced P-substrate CMOS technology with Shallow Trench Isolation (STI). N-type diffusions form the Drain 301 and Source 302 of the NMOS device, and are separated by Poly-silicon (usually called “poly”) that forms the gate 303. A P-type diffusion forms the bulk tap 304, allowing connection to the P-well 305. The Pwell has low resistance, and it is electrically connected to the high-resistance P-sub 312 underneath. STI 311 separates the bulk tap 304 from the area of the drain 301, source 302, and gate 303. Metallic contacts 306, 307, and 308 connect to the Drain 301, Source 302, and Bulk tap 304, allowing connection to the rest of the circuit. A parasitic NPN transistor 309 is a bulk device formed from the Drain, Bulk and Source of the NMOS device (shown in FIG. 2), while the parasitic resistance 310 connects the base of the NPN device to the bulk tap 304.
FIG. 4 illustrates an idealized I-V curve of the NMOS snapback device of FIG. 3. During the ESD event, current discharged into the device suddenly increases the voltage on the Drain. This causes avalanche multiplication of current across the Drain/Bulk junction, which causes current to be injected into the substrate. This current in turn builds up a voltage across the parasitic resistance 310 (shown in FIG. 3) until the Bulk/Source junction becomes forward-biased, turning the NPN device on. This happens at a voltage and current given by VT1 and IT1, known as the snapback trigger point. After the NPN turns on, the voltage across the device drops to VH, known as the Hold Voltage while current flows directly from the Drain to the Source. The avalanche multiplication current continues to flow, maintaining the snapback. As the current continues to increase, the voltage across the device increases according to the device on resistance, RON. Eventually, the power dissipation within the device reaches the point (VT2, IT2) at which the heat generated by the ESD current causes thermal breakdown, also known as the second breakdown point. At this point, the device has reached its thermal limits, and undergoes destructive breakdown.
Several parameters define the ESD Region in which the ESD protection device must operate. First, the VH must be greater than the power rail voltage (VDD) plus some margin. The amount of margin necessary is dependent on power supply tolerances and also conditions the circuit may be subjected to during product testing. The protection device must also clamp the voltage below the oxide breakdown voltage (VMAX) throughout the duration of the ESD event. Furthermore, the protection must survive up to the desired ESD protection level (IMAX). The locations of the various points in FIG. 4 are highly dependent upon several factors, including edge rate of the ESD event, dopant densities, physical dimensions, the circuitry connected to the gate, and the substrate resistance 310 (shown in FIG. 3).
FIG. 5a is a top view of a conventional ESD protection device including a snap-back device as a discharge circuit. One of the most fundamental ways of controlling snap-back hold voltage VH and VT1 is by varying a space 500 between the discharge circuit and the tie-down diffusion of the well as shown in FIG. 5a. FIG. 5b is a cross sectional view of the ESD protection device shown in FIG. 5a. By controlling the space 500 between the tie-down diffusion 501 of Pwell 502 and the emitter 503 of the bipolar transistor 504, the RBULK resistance 505 can also be controlled. By increasing the space 500, which is part of the size of Pwell 502, the value of RBULK is increased. An increased RBULK allows for a greater voltage drop in the substrate for a given current, which has two beneficial effects. The first benefit is that the necessary VBE (Base-Emitter Voltage) for triggering the snapback can be more easily achieved, which can lower the VT1 of the snap-back. The second benefit is that, during snapback, the bipolar transistor will be turned on harder as the VBE will be raised further above the threshold voltage, which reduces the hold voltage VH.
FIG. 6a illustrates a top view of another device commonly used for ESD clamps known as the Silicon-Controlled Rectifier (SCR). An example of such an SCR device is disclosed in U.S. Pat. No. 5,012,317. FIG. 6b is a cross sectional view of the SCR device shown in FIG. 6a. The discharge circuit in an SCR device includes two parasitic bipolar transistors, a PNP 600 and an NPN 601 as shown in FIG. 6b. The PNP bipolar transistor 600 is formed by P+ diffusion 602, Nwell 603, and Pwell 604. The NPN bipolar transistor 601 is formed by Nwell 603, Pwell 604, and N+ diffusion 605. The SCR device has a large current conduction ability that is potentially higher than snapback devices. FIG. 6c is circuit schematic illustrating the SCR circuit of FIG. 6b connected between a circuit pad and VSS, when in operation.
Two of the important metrics to be optimized in an SCR device are the activation and holding voltages, which are directly analogous to the snap-back VT1 and VH of FIG. 4. The activation and holding voltages of the SCR can be controlled by varying the space 606 shown in FIG. 6b to the tie-down diffusion 607 of Pwell 604. This in turn varies the resistance RBULK 608. A higher resistance corresponds to lower activation and holding voltages. Hence it is possible to reduce the activation and holding voltages by increasing the space to the Pwell pick-up.
Unlike the snapback device, the self-triggering voltage for a typical SCR is typically in the 10-20V range, which is too high for the majority of applications in fine-geometry ICs. In order to overcome this limitation, SCRs require a trigger circuit to turn on during the ESD event, which complicates the design significantly. In addition, SCRs normally require more simulation and testing than snapback devices, which also complicates their use.
The main problem with both the snapback and the SCR devices of the prior art is that the well resistance is so low, due to high doping, that a significant space is required to obtain a sufficient increase in RBULK. As a result of this, increasing the performance of the ESD protection device would automatically impact the area of the device and the speed of the signal inputted to the IC.
It is, therefore, desirable to provide a structure that allows for increasing the sensitivity and performance of the ESD protection device without increasing its size.